The Ethernet network is a well-known communication network and is considered by many as the most popular LAN system in use today. In general, the Ethernet network provides for communication of computer data amongst user nodes attached to the network. A 10-Base Ethernet system operates to transmit data packets from a source address to a destination address at a speed of 10 Mbit per second. A faster system is the 100-Base Ethernet system which similarly operates to transmit data packets from a source address to a destination address but at a speed of 100 Mbit per second. It should be noted, however, that the traditional Ethernet network is a bus type topology. As such, the Ethernet network has been traditionally confined to LAN applications. For example, the 10/100-Base Ethernet bus is typically limited to approximately 100 feet from node to node, such as for use in small buildings and the like.
In recent years there has been attempts to expand the capabilities of LANs in general to wide area network applications such as through the use of, Asynchronous Transfer Mode (ATM) system technology. However, adapting ATM for LAN use is considered complex and would involve significant software changes and complicated protocol management.
On the other hand, another generally known form of wide area network application technology is the T1/E1 High Speed Data Subscribe Line (HDSL) technology developed by AT&T. T1/E1 HDSL technology uses twisted pair transmission lines, much like that of the standard telephone line from the telephone company local central office to the subscriber, but can reach transmission speeds of up to 2 MHz.
In order to be able to interface between a 10/100-Base Ethernet system and a T1/E1 HDSL system, there have been recent attempts to develop bridging devices. Referring to FIG. 1, there is shown such a prior art bridging device which uses the known "store and forward technique".
When transmitting over the Ethernet a "frame" or "packet" is utilized. The packet is a series of bits forming a complete unit of information that is sent across a network. The typical packet has a 62 bit preamble, a 2 bit start of frame delimiter, 6 byte destination address, 6 byte source address, 64-1500 bytes data field, and 4 bytes cyclical redundancy code (CRC). There is typically a 96 bit gap between packets.
In FIG. 1 there is depicted in a simplified block diagram form is prior art bridge device 10 coupling one line Ethernet port 12 to T1/E1 HDSL line 14. Bridge device 10 includes CPU 16 coupled to main memory 18 over CPU/memory bus 20. Ethernet port 12 and memory to T1/E1 HDSL interface 22 are also coupled to CPU/memory bus 20. T1/E1 HDSL interface 24 interconnects between memory to T1/E1 HDSL interface 22 and T1/E1 HDSL line 14. Ethernet port 12 is coupled to a 10/100-Base Ethernet line 26 through respective physical layer (PHY) 28. PHY 28 translates the Ethernet wire signal to the TTL digital level in the well-known Ethernet protocol hierarchy and provides for clock recovery of the intermixed clock/data transmitted over Ethernet line 26. Ethernet port has Media Access Controller (MAC) 30, such as the Digital Equipment Corporation model DC21143, whose characteristics are set forth in the DECchip 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual dated October 1995 and is incorporated here by reference. MAC 30 processes the packets being transmitted/received by the port.
The typical Ethernet operates as follows. Using port 12 as a port receiving data from the Ethernet wire, PHY 28 filters out the clock to obtain the desired packet. MAC 30 would then receive the incoming packet and copy it to main memory 18 over bus 20 in accordance with the CPU/memory bus protocol. CPU 16 would read main memory 18. CPU 16 then initiates having the packet copied from main memory 18 to Memory to T1/E1 HDSL interface 22 which translates the packet into T1/E1 HDSL protocol frame format and sends the translated packet to T1/E1 HDSL interface 24 for transmission on T1/E1 HDSL line 14. A similar process occurs when T1/E1 HDSL line 14 has information to be received by Ethernet port 12 for transmission over Ethernet line 26.
This typical Ethernet bridge has latency problems. The store and forward approach under CPU control takes significant compute time to process the packet from Ethernet port 12, to main memory 18, and then to respective T1/E1 HDSL interfaces 22, 24 before a properly formatted frame is sent over T1/E1 HDSL line 14. Therefore, there is a still a need to be able to extend the Ethernet into wide area network applications using a simple to implement high performance device which maintains control over the data flow recognizing the speed difference between T1/E1 HDSL transmission (2 Mbit per second) and Ethernet transmission (10/100 Mbit per second). The embodiments of the present invention provide such a system.